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iSaSiLk 5.107 released!

13/12/2017

iSaSiLk 5.107 has improved its countermeasure against variants of the PKCS#1 Bleichenbacher attack and adds support for the application layer protocol negotiation  (ALPN) extension!

IAIK-JCE 5.5 released!

29/08/2017

IAIK-JCE 5.5 fixes a signature algorithm name incompatibility in JSSE algorithm constraint checking, implements SHA-3 based signature and HMAC algorithms, and adds throughout support for using the IAIK provider without the necessity of installing it within the JCA/JCE Security framework.

References

Our Clients


High-performance NIST P-256/P-384 ECC Module

High-performance NIST P-256/P-384 ECC module

  • Fully tested using an ASIC and an FPGA design-flow
  • FIPS PUB 186-3 Digital Signature Standard compliant
  • AMBA Advanced Peripheral Bus (APB) as interconnection to other modules
  • Fully based on Registers (no Latches or RAM macros were used)
  • Every field operation manually executable (for future compatibility)
  • Supports fixed runtime EC point multiplication and EC point addition
  • Comes with functional SystemC model for high-performance simulation

Further technical, sales, and pricing information:

Please contact sales@iaik.tugraz.at for any further information.

Area and performance figures:

Parameter

Unit

P-256 only

P-256 & P-384

ASIC (90nm)

 

 

 

Area @ 100MHz

GE

70,122

114,438

Max frequency

MHz

416

344

Area @ max freq.

GE

115,968

172,557

Max throughput

PM/sec

1,860

721

ASIC (180nm)

 

 

 

Area @ 100MHz

GE

82,225

137,319

Max frequency

MHz

192

161

Area @ max freq.

GE

111,620

162,400

Max throughput

PM/sec

858

337

FPGA Virtex-II pro

 

 

 

Area

Slices (RAMB16s)

10,500

18,900

Max frequency

MHz

76

73

FPGA Virtex 4

 

 

 

Area

Slices (RAMB16s)

10,300

17,200

Max frequency

MHz

80

83

FPGA Virtex 6

 

 

 

Area

Slices (RAMB36s)

3,700

7,100

Max frequency

MHz

86

80

FPGA Zynq-7000

 

 

 

Area

Slices (RAMB36s)

3,500

7,100

Max frequency

MHz

88

79

FPGA Cyclone III

 

 

 

Area

LEs (BM-kbits)

21,400

34,500

Max frequency

MHz

54

55

FPGA Cyclone IV

 

 

 

Area

LEs (BM-kbits)

20,500

35,900

Max frequency

MHz

54

59

FPGA Cyclone V

 

 

 

Area

ALUTs (BM-kbits)

11,200

18,800

Max frequency

MHz

57

56

FPGA Arria II GX

 

 

 

Area

ALUTs (BM-kbits)

11,800

18,600

Max frequency

MHz

55

54

PM = Point Multiplications

The hardware results were generated using the following tools:

  • ASIC results
    • Cadence(R) Encounter(R) RTL Compiler v08.10-s238_1
    • Cadence(R) First Encounter(R) 08.10-s273_1 (64bit)
      • UMC L090N technology using Faraday f090SP standard cell library (FSD0A_A), 3.136 µm²/GE; worst case conditions (temperature 125°C, core voltage 0.9V)
      • UMC L180GII technology using Faraday f180 standard cell library (FSA0A_C) , 9.3744 µm²/GE; worst case conditions (temperature 125°C, core voltage 1.62V)
  • FPGA results¹
    • Xilinx Release 10.1 – xst K.39 (lin64)
      • Xilinx Virtex-II pro, xc2vp70-ff1517-7
    • Xilinx Release 14.1 - xst P.15xf (lin64)
      • Xilinx Virtex-4, xc4vlx100-ff1148-12
      • Xilinx Virtex-6 ML605 evaluation platform, xc6vlx240t-ff1156-1
      • Xilinx Zynq-7000, xc7z020-clg400-1
    • Altera Quartus II 11.1 SP2
      • Altera Cyclone III FPGA, ep3c40f324c6
      • Altera Cyclone IV FPGA, ep4ce55f23c6
      • Altera Cyclone V FPGA², 5cgxfc7c6f23c6
      • Altera Arria II GX FPGA, ep2agx45cu17i3

¹ Note that the area results are not directly comparable among the different FPGAs, as slices (e.g. Virtex-4 and Virtex-6), logic elements (LEs), and adaptive look-up tables (ALUTs) are significantly different basic units.

² Note that the timing models used during TimeQuest timing analysis of Altera Cyclone V FPGAs are preliminary in Quartus II Version 11.1b259SP2.11.

 

 
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