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iSaSiLk 5.107 released!

13/12/2017

iSaSiLk 5.107 has improved its countermeasure against variants of the PKCS#1 Bleichenbacher attack and adds support for the application layer protocol negotiation  (ALPN) extension!

IAIK-JCE 5.5 released!

29/08/2017

IAIK-JCE 5.5 fixes a signature algorithm name incompatibility in JSSE algorithm constraint checking, implements SHA-3 based signature and HMAC algorithms, and adds throughout support for using the IAIK provider without the necessity of installing it within the JCA/JCE Security framework.

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Our Clients


Combined Module SHA-224 and SHA-256

The IAIK combined SHA-224 and SHA-256 modules are fully compliant to the FIPS PUB 180-3 Secure Hash Standard definition. We offer three different versions of the module that vary in size and throughput. All of them come with a standard 32-bit bus interface, an easily accessible memory mapped interface and have been evaluated for both ASIC and FPGA designs. We also provide a fully functional SystemC model which can be used for high-performance simulations.

Features:

  • Fully tested using an ASIC and an FPGA design-flow
  • SystemC model for high-performance simulations
  • FIPS PUB 180-3 Secure Hash Standard compliant
  • AMBA Advanced Peripheral Bus (APB) as interconnection to other modules
  • Fully based on Registers (no Latches or RAM macros were used)

 
Deliverables:

  • VHDL source code
  • TCL-testbench (Modelsim, Cadence)
  • Scripts for synthesis & simulation
  • Documentation

 
Performance:

The hardware results were generated using the following tools:

  • Faraday UMC f090SP design technology (fsd0a_a_generic_core_tt1v25c 2009Q2v2.0). 3.136 μm²/GE. Worst Case Conditions (125°C and 0.9V supply)
  • Encounter(R) RTL Compiler v08.10-s238_1
  • First Encounter 08.10-s273_1 (64bit)
  • Xilinx Release 12.4 - xst M.81d (lin64) (using FPGA xc6vcx240t-ff1156-1)

Parameter

Unit

Area

Native

Speed x2

Speed x4

Writing of message

Cycles

 16

 16

 16

 16

Cycles for computation

Cycles

 656

 66

 34

 18

Total cycles per block

Cycles

 672

 82

 50

 34

Message Throughput @ 100MHz

MByte/sec

 9.5

 78

 128

 188

Message Throughput @ 100MHz

MBit/sec

 76

 624

 1024

 1505

ASIC

 

 

 

 

 

Module @ 100MHz

GE

 9,339

 17,234

 19,649

 26,810

Area @ 100MHz

GE

 9,762

 18,819

 21,201

 28,358

Power @ 100MHz

mW

 1.879

 3.464

 5.449

 7.421

Max frequency

MHz

 600

 450

 330

 192

Area @ max frequency

GE

 11,483

 24,257

 28,688

 39,566

Max throughput

MByte/sec

 57

 351

 422

 361

Max throughput

Mbit/sec

 457

 2810

 3379

 2891

FPGA

 

 

 

 

 

Area

LUTs

 866

 2,659

 3,803

 5,461

Max frequency

MHz

 198

 150.5

 85.7

 46.0

Further technical and sales information:

Please contact sales@iaik.tugraz.at for any further information.

Prices:

Please see our price list.

 

 
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